CS501 Grand Quiz Solution 2020
CS501 Grand Quiz Solution 2020 Question No: 1 For
any of the instructions that are a part of the instruction set of the SRC,
there are cerain_________required; which be used to select the appropriate function
for the ALU to be performed, to select the appropriate registers, or the
appropriate memory location. ►Register ►Control signals (Page 171) ►Memory ►None
of the given Question No: 2 – FALCON-A
processor bus has 16 lines or is 16-bits wide while that of SRC _____wide. ►8-bits ►16-bits ►32-bits (Page 157) ►64-bits Question No: 3 – What
is the instruction length of the FALCON-A processor? ►8-bits ►16-bits (Page 134) ►32-bits ►64-bits Question No: 4 – _________control
signals enable the input to the PC for receiving a value that is currently on
the internal processor bus. ►LPC (Page 172) ►INC4 ►LC ►I Question No: 5 – Which
one of the following is a bi-stable device, capable of storing one bit of
information? ►Decoder ►Flip-Flop
(Page 76) ►Multiplexer ►Diplexer Question No: 6 – Which
instruction is used to store register to memory using relative address? ►ld
instruction ►ldr
instruction ►lar
instruction ►str instruction (Page 48) Question No: 7 – Which
field of the machine language instruction is the “type of operation” that is
to be performed? ►Op-code
(Page 33) ►CPU
registers ►Momory
cells ►I/O
locations Question No: 8 – The
instruction ___________ will load the register R3 with the contenets of the
m\emory location M [PC+56] ►Add
R3, 56 ►lar
R3, 56 ►ldr R3, 56 (Page 56) ►str
R3, 56 Question No: 9 – _______
operation is required to change the processor’s state to a known, defined
value. ►Change ►Reset (Page 194) ►Update ►None
of the given Question No: 10 – which
type of instructions help in changing the flow of the program as and when required? ►Arithmetic ►Control (Page 137) ►Data
transfer ►Floating
point Question No: 11 – Which
one of the following registers holds the address of the next instruction to
be executed? ►Accumulator ►Address
Mask ►Instruction
Register ►Program Counter (Page 151) Question No: 12 – Which
one of the following is the memory organization of EAGLE processor? ►8-bits (Page 112) ►16-bits ►32-bit ►64-bits Question No: 13 – The
external interface of FALCON-A consists of a ______address bus and ______a
data bus. ►8-bit.
8-bit ►16-bit. 16-bit
►16-bit.
24-bit ►16-bit.
32-bit Question No: 14 – Type
A of SRC has which of the following instructions? A)
andi, instruction b)
No operation or nop instruction c)
lar instruction d)
ldr instruction e)
Stop operation or stop instruction ►&
(b) ►(b)
& (c) ►&
(e) ►(b) & (e) (Page 47) Question No: 1 – What is the instruction length of the SRC processor? ►
8 bits ►
16 bits ► 32 bits
(Page 134) ►
64 bits Question No: 2 – Which one of the following is the memory organization
of FALCON-E processor? ► 28 *
8 bits ► 216 * 8
bits (Page 112) ► 232 *
8 bits ► 264 *
8 bits Question No: 3 – “If P = 1, then load the contents of register R1 into register
R2”. This statement can be written in RTL as: ►
R1 ¬ R2 ►
P: R1 ¬ R2 ►
P: R2 ¬ R1, P: R1 ¬ R2 Question No: 4 – The instruction —————will load the register R3 with the contents of
the memory location M [PC+56] ► Add R3, 56 ► lar R3, 56 ► ldr
R3, 56 (Page 47) rep ► str R3, 56 Question No: 5 – ———-are
faster than cache memory ► Accumulator register ► CPU
registers (Page 33) ► I/O devices ► ROM Question No: 6 – P: R3 ¬ R5 MAR ¬ IR These
two are instructions written using RTL .If these two operations is to occur
simultaneously then which symbol will we use to separate them so that it
becomes a correct statement with the condition that two operations occur
simultaneously? ►
Arrow ¬ ►
Colon : ► Comma
, (Page 69) ►
Parentheses () Question No: 7 – Prefetching
can be considered a primitive form of————- ► Pipelining
(Page
42) ► Multi-processing ► Self-execution ► Exception Question No: 8 – The
processor must have a way of saving information about its state or context so
that it can be restored upon return from the ————- ► Exception ► Function ► Stack ► Thread Question No: 9 – Which
one of the following circuit design levels is called the gate level? ► Logic
Design Level (Page 22) ► Circuit Level ► Mask Level ► None of the given Question No: 10 – __________ enable the input to the PC for receiving a value
that is currently on the internal processor bus. ► LPC
(Page 172) rep ►
INC4 ►
LC ►
Cout Question No: 12 – There
are _________ types of reset operations in SRC ► Two
(Page 195) ►
Three ►
Four ►
Five Question No: 13 – _____________
controller controls the sequence of the flow of microinstructions. ►
Multiplexer ►
Microprogram (Page 225) ►
ALU ►
None of the given Question No: 14 – FALCON-A
processor bus has 16 lines or is 16-bits wide while that of SRC is __________
wide. ►
8-bits ►
24-bits ►
32-bits (Page
157) REP ►
64-bits Question No: 15 – Which of the following statement(s) is/are correct about Reduced
Instruction Set Computer (RISC) architectures. (i)
The typical RISC machine instruction set is small, and is usually a subject
of a CISC instruction set. (ii)
No arithmetic or logical instruction can refer to the memory directly. (iii)
A comparatively large number of user registers are available. (iv)
Instructions can be easily decoded through hard-wired control units. ►
(i) and (iii) only ►
(i), (iii) and (iv) ►
(i), (ii) and (iii) only ►
(i),(ii),(iii) and (iv) Question No: 16 – Which
one of the following register holds the instruction that is being executed? ►
Accumulator ►
Address Mask ► Instruction
Register (Page 152) ►
Program Counter CS501-Advance
Computer Architecture Midterm
Special 2006 Question No: 1 – _____________all
memory systems are dumb, in that they respond to only two commands: read or
write Virtually
Computer
Systems Design And Architecture, 2/E Logically Physically None
of These Question No: 2 – To
access an operand in memory, the CPU must first generate an address, which it
then issues to the __________ MEMORY
Computer
Systems Design And Architecture, 2/E REGISTER DATA
BUS ALL
OF ABOVE Question No: 3 – ___________
or Branch instructions affect the order in which instructions are performed,
or control the flow of the program Control
Computer
Systems Design And Architecture, 2/E DATA
MOVMENT Arithmetic LOGICAL MIDTERM EXAMINATION FALL
2006 CS501
– ADVANCE COMPUTER ARCHITECTURE Question No: 1 – The
code size of 2-address instruction is ________________. ►
5 bytes ► 7 bytes (Page 36) ►
3 bytes ►
2 bytes Question No: 2 The
data movement instructions ___________ data within the machine and to or from
input/output devices. ►
Store ►
Load ►
Move ► None of Above (Page 141) Question No: 3 – Register-register
instructions use ____________ memory operands out of a total of 3 operands ►
1 ►
3 ► 0 (Page 37) ►
2 Question No: 4 – _____________all
memory systems are dumb, in that they respond to only two commands: read or
write. ► Virtually Computer Systems Design And Architecture,
2/E Rep ►
Logically ►
Physically ►
None of Above Question No: 5 – Flip-flop
is a ____________device, capable of storing one bit of Information ► Bi-stable (Page 76) ►
Unit-stable ►
Stable ►
Storage Question # 1 of 10 – In
which one of the following addressing modes, the value to be stored in memory
is obtained by directly retrieving it from another memory location? ►Immediate
addressing mode ►Indirect
Addressing Mode ►Register
(Direct) Addressing Mode Question # 2 of 10 – Execution
time of a program with respect to the processor is calculated as: ►Execution
Time = IC x CPI x MIPS ►Execution Time = IC x CPI x
T (Page
254) ►Execution
Time = CPI x T x MFLOPS ►Execution
Time = IC x T Question # 3 of 10 – An
“assembler” that runs on one processor and translates an assembly language
program written for another processor into the machine language of the other
processor is called a —————- ►compiler ►cross assembler (Page 26) ►debugger ►linker Question # 4 of 10 – What
functionality is performed by the instruction “lar R3, 36” of SRC? ►It
will load the register R3 with the contents of the memory location M [PC+36] ►It will load the register R3 with the
relative address itself (PC+36). (Page 48) ►It
will store the register R3 contents to the memory location M [PC+36] ►No
operation Question # 5 of 10 – Which
operator is used to ‘name’ registers, or part of registers, in the Register
Transfer Language? Select
correct option: ►:= (Page 66) ►& ►% ►© Question # 6 of 10 – What
is the working of Processor Status Word (PSW)? ►To hold the current status of the
processor. (Page 28) ►To
hold the address of the current process ►To
hold the instruction that the computer is currently processing ►To
hold the address of the next instruction in memory that is to be executed Question # 7 of 10 – Almost
every commercial computer has its own particular ———- language ►3GL ►English
language ►Higher
level language ►assembly language (Page 25) Question # 8 of 10 – In
which of the following instructions the data move between a register in the
processor and a memory location (or another register) and are also called data
movement? ►Arithmetic/logic ►Load/store (Page 141) ►Test/branch ►None
of the given Question # 9 of 10 – What
functionality is performed by the instruction “str R8, 34” of SRC? ►It
will load the register R8 with the contents of the memory location M [PC+34] ►It
will load the register R8 with the relative address itself (PC+34).
►It will store the register R8 contents to the memory location M
[PC+34] (Page 48) ►No
operation Question # 10 of 10 – What
does the instruction “ldr R3, 58” of SRC do?
►It will load the register R3 with the contents of the memory location M
[PC+58] (Page 47) ►It
will load the register R3 with the relative address itself (PC+58). ►It
will store the register R3 contents to the memory location M [PC+58] ►No
operation 1 (23--) Question # 1 of 10 – Which
one of the following is the highest level of abstraction in digital design in
which the computer architect views the system for the description of system
components and their interconnections? ►Processor-Memory-Switch level (PMS
level) (Page 22) Question # 2 of 10 – Which
of the instruction is used to load register from memory using a relative
address? ►ld instruction Question # 3 of 10 – For
the __________ type instructions, we require a register to hold the data that
is to be loaded from the memory, or stored back to the memory ►Jump ►Control ►load/store
(Page
89) ►None
of the given Question # 4 of 10 – The
CPU includes three types of instructions, which have different operands and
will need different representations. Which one of the instructions requires
two source registers? ►Jump
and branch format instructions ►Immediate
format instructions 2
( 07, ) Question # 1 of 10 – ►2^8 bytes Question # 2 of 10 – ►IR<16..0> Question # 3 of 10 – ►Address Question # 4 of 10 – Identify the opcode, destination register (DR), source
registers (SA and SB i/e source register A and source register B) from the
following example. ADD R1, R2, R3 Question # 5 of 10 – What
does the word ‘D’ in the ‘D-flip-Flop’ stands for? ►Data Question # 6 of 10 – ►4 bytes, 7 bytes Question # 7 of 10 – Question # 8 of 10 – Whic of the following statements is/are true about RISC
processors’ claimed advantages over CISC processors? (a) Keeping regularly
accessed variables in registers as opposed to keeping them in memory
facilitates faster execution. (b) RISC CPUs outperform CISC CPU’s in
procedural programming environments. (c) Instruction pipelining has helped
RISC CPU’s to attain a target of 1 cycle per instruction. (d) It is easier to
maintain the “family concept” in RISC CPUs. Question # 9 of 10 – Which
one of the following is/are the features of Register Transfer Language? a)
It is a symbolic language b)
It is describing the internal organization of digital computers c)
It is an elementary operation performed (during one clock pulse), on the
information stored in one or more registers d) It is high level language Question # 10 of 10 – ►CISC
(Page 148) Question # 1 of 10 – ►Accumulator ►8-bit ►Perfecting ►Backward compatibility ►INC4 ►Accumulator Question # 7 of 10 – ►Time to execute a program or program mix Question # 8 of 10 – Which
one of the following register(s) that is/are programmer invisible and is/are
required to hold an operand or result value while the bus is busy
transmitting some other value? ►Instruction Register ►Control (not sure) Question # 10 of 10 – Which
one of the following register(s) contain(s) the address of the place the CPU
wants to work with in the main memory and is/are directly connected to the
RAM chips on the motherboard? ►Instruction Register 2 07, Question
# 1 of 10 ( Start time: 10:02:48 PM ) Total Marks: 1 2^8 bytes Question
# 2 of 10 ( Start time: 10:03:58 PM ) Total Marks: 1 IR<16..0> Question
# 3 of 10 ( Start time: 10:04:28 PM ) Total Marks: 1 To hold the current status of the processor.
Ans Question
# 4 of 10 ( Start time: 10:05:10 PM ) Total Marks: 1 It will load the register R3 with the contents of the memory
location M [PC+58]
Ans Question
# 5 of 10 ( Start time: 10:06:34 PM ) Total Marks: 1 8 bits Question
# 6 of 10 ( Start time: 10:06:57 PM ) Total Marks: 1 Address Question
# 8 of 10 ( Start time: 10:07:36 PM ) Total Marks: 1 Jump Question
# 9 of 10 ( Start time: 10:08:08 PM ) Total Marks: 1 Processor-Memory-Switch level (PMS level)
Ans Question
# 10 of 10 ( Start time: 10:08:50 PM ) Total Marks: 1 Opcode= R1, DR=ADD, SA=R2, SB=R3 Question
# 1 of 10 ( Start time: 10:20:53 PM ) Total Marks: 1 Logic Design Level
Ans Question
# 2 of 10 ( Start time: 10:21:17 PM ) Total Marks: 1 Jump and branch format instructions Question
# 5 of 10 ( Start time: 10:24:08 PM ) Total Marks: 1 Parentheses () Question
# 6 of 10 ( Start time: 10:25:09 PM ) Total Marks: 1 Arithmetic/logic What
does the word ‘D’ in the ‘D-flip-Flop’ stands for? Data Question
# 9 of 10 ( Start time: 10:27:24 PM ) Total Marks: 1 Add R3, 56 Question
# 10 of 10 ( Start time: 10:28:07 PM ) Total Marks: 1 8 bits Question
# 2 of 10 ( Start time: 10:41:07 PM ) Total Marks: 1 4 bytes, 7 bytes Question
# 3 of 10 ( Start time: 10:41:57 PM ) Total Marks: 1 Address Question
# 4 of 10 ( Start time: 10:42:17 PM ) Total Marks: 1 :=
Ans Question
# 5 of 10 ( Start time: 10:42:37 PM ) Total Marks: 1 2^8 bytes Question
# 7 of 10 ( Start time: 10:43:25 PM ) Total Marks: 1 compiler Question
# 9 of 10 ( Start time: 10:44:37 PM ) Total Marks: 1 It will load the register R3 with the contents of the memory
location M [PC+58]
Ans Question # 3 of 10 ( Start time: 11:07:32 PM ) Total
Marks: 1 Question # 5 of 10 ( Start time: 11:09:24 PM ) Total
Marks: 1 Question # 8 of 10 ( Start time: 11:11:44 PM ) Total
Marks: 1 Question # 9 of 10 ( Start time: 11:12:32 PM ) Total
Marks: 1 Question # 10 of 10 ( Start time: 11:14:04 PM ) Total Marks:
1 Question
# 3 of 10 ( Start time: 08:03:34 PM ) Total Marks: 1 CISC Ans Question
# 5 of 10 ( Start time: 08:05:09 PM ) Total Marks: 1 Accumulator Question
# 10 of 10 ( Start time: 08:09:02 PM ) Total Marks: 1 8-bit Question
# 1 of 10 ( Start time: 08:18:13 PM ) Total Marks: 1 Accumulator Question
# 2 of 10 ( Start time: 08:18:29 PM ) Total Marks: 1 Perfecting
Ans Question
# 3 of 10 ( Start time: 08:18:52 PM ) Total Marks: 1 LPC Ans Question
# 4 of 10 ( Start time: 08:19:03 PM ) Total Marks: 1 Exception
Ans Question
# 5 of 10 ( Start time: 08:20:13 PM ) Total Marks: 1 Backward compatibility Question
# 6 of 10 ( Start time: 08:20:40 PM ) Total Marks: 1 INC4 Question
# 7 of 10 ( Start time: 08:21:15 PM ) Total Marks: 1 Accumulator Ans Question
# 8 of 10 ( Start time: 08:21:49 PM ) Total Marks: 1 Time to execute a program or program mix 8-bit Question
# 10 of 10 ( Start time: 08:22:19 PM ) Total Marks: 1 Instruction Register Question
# 1 of 10 ( Start time: 08:24:34 PM ) Total Marks: 1 Control Question
# 2 of 10 ( Start time: 08:25:17 PM ) Total Marks: 1 INC4 Question
# 3 of 10 ( Start time: 08:25:30 PM ) Total Marks: 1 8-bit , 8-bit Question
# 4 of 10 ( Start time: 08:25:50 PM ) Total Marks: 1 Backward compatibility Question
# 5 of 10 ( Start time: 08:26:02 PM ) Total Marks: 1 Accumulator Ans Question
# 6 of 10 ( Start time: 08:26:41 PM ) Total Marks: 1 Instruction Register Question
# 7 of 10 ( Start time: 08:27:38 PM ) Total Marks: 1 8-bits Question
# 8 of 10 ( Start time: 08:27:54 PM ) Total Marks: 1 LPC Ans Question
# 9 of 10 ( Start time: 08:28:10 PM ) Total Marks: 1 8-bit Which
one of the following is the memory organization of EAGLE processor? 2^8
* 8 bits 2^16 * 8 bits Ans 2^32
* 8 bits 2^64
* 8 bits Question
# 1 In
which of the following addressing modes, the operand does not specify an
address but it is the actual data to be used. Direct Indirect Immediate
Ans Relative Question
# 2 Which
one of the following registers holds the address of the next instruction to
be executed? Accumulator Address
Mask Instruction
Register
Ans Program
Counter Question
# 3 In
which of the following techniques, the time a process spends waiting for
instructions to be fetched from memory is minimized? Prefecting Pipelining Superscalar
operation Ans Speedup Question
# 4 The
external interface of FALCON-A consists of
a address bus. 8-bit 16-bit
Ans 24-bit 32-bit Question
# 5 Which
one of the following is the memory organization of EAGLE processor? 2^8*8
bits 2^16*8
bits
Ans 2^32*8
bits 2^64*8
bits Question
# 7 The
External interface of FALCON-A consists of
a address bus and
a data bus. 8bit,
8bit 16-bit,16-bit
Ans 16-bit,24-bit 16-bit,
32-bit Question
# 8 Computer
system performance is usually measured by the Time
to execute a program or program mix The
speed with which it executes programs Ans Processor’s
utilization in solving the problems Instructions
that can be carried out simultaneously Question
# 9 Which
one of the following registers holds the instruction that is being executed? Accumulator Address
Mask Instruction
Register
Ans Program
Counter Question
# 10 Matorola MC68000
is an example of microprocessor. Cisc
Ans Risc SRC dentify the opcode, destination register (DR), source
registers (SA and SB i/e source register A and source register B) from the following example. ADD R1, R2, R3 Opcode= R1, DR=ADD, SA=R2, SB=R3 Almost
every commercial computer has its own particular ———- language 3GL Which
one of the following is a binary cell capable of storing one bit of
information? Decoder Which
statement(s)from the following is/are correct about Reduced Instruction Set
Computer (RISC) architectures. (i) The
typical RISC machine instruction set is small, and is usually a subject of a
CISC instruction set. (ii) (ii)
No arithmetic or logical instruction can refer to the memory directly. (iii) (iii)
A comparatively large number of user registers are available. (iv) (iv)
Instructions can be easily decoded through hard-wired control units. (i)
and (iii) only What
is the instruction length of the FALCON-E processor? 8 bits Which
one of the following are the code size and the Number of memory bytes
respectively for a 3-address instruction? 0 bytes, 10 bytes The
CPU includes three types of instructions, which have different operands and
will need different representations. Which one of the instructions requires
two source registers? Select
correct option: Jump
and branch format instructions Which
one of the following are the code size and the Number of memory bytes
respectively for a 2-address instruction? 4 bytes, 7 bytes Nadia: P:
R3 <- R5 MAR <- IR These two are instructions written using RTL .If
these two operations is to occur simultaneously then which symbol will we use
to separate them so that it becomes a correct statement with the condition
that two operations occur simultaneously? Parentheses
() In
which of the following instructions the data move between a register in the
processor and a memory location (or another register) and are also called
data movement? Arithmetic/logic In
which one of the following addressing modes, the operand does not specify an
address but it is the actual data to be used. Direct Which
one of the following portions of an instruction represents the operation to
be performed? Address ====================================================================== 1 1 MIDTERM EXAMINATION Fall 2011 Question No: 9 – _______
operation is required to change the processor‟s state to a known, defined
value. ►Change ►Reset (Page 194) ►Update ►None
of the given Question No: 11 – Which
one of the following registers holds the address of the next instruction to
be executed? ►Accumulator ►Address
Mask ►Instruction
Register ►Program Counter (Page 151) Question No: 12 – Which
one of the following is the memory organization of EAGLE processor? ►8-bits (Page 112) ►16-bits ►32-bit ►64-bits Question No: 13 – The
external interface of FALCON-A consists of a ______address bus and ______a
data bus. ►8-bit.
8-bit ►16-bit. 16-bit ►16-bit.
24-bit ►16-bit.
32-bit Question No: 14 – Type
A of SRC has which of the following instructions? 1. A) andi,
instruction 2. b) No operation or
nop instruction 3. c) lar instruction 4. d) ldr instruction 5. e) Stop operation
or stop instruction ►&
(b) ►(b)
& (c) ►&
(e) ►(b) & (e) (Page 47) 4 MIDTERM EXAMINATION Spring 2010 (Session – 5) Question No: 1 – What is the instruction length of the SRC processor? ►
8 bits ►
16 bits ► 32 bits (Page 134) ►
64 bits Question No: 2 – Which one of the following is the memory organization
of FALCON-E processor? ►
28 * 8 bits ► 216 * 8 bits (Page 112) ►
232 * 8 bits ►
264 * 8 bits Question No: 3 – “If P = 1, then load the contents of register R1 into register
R2”. This statement can be written in RTL as: ►
R1 ¬ R2 ►
P: R1 ¬ R2 ► P: R2 ¬ R1 (not confirms) ►
P: R2 ¬ R1, P: R1 ¬ R2 Question No: 4 – The instruction —————will load the
register R3 with the contents of the memory location M [PC+56] (Page 47) rep Question No: 5 – ———-are
faster than cache memory ► ► (Page 33) ► ► 5 Question No: 6 – P: R3 ¬ R5 MAR ¬ IR These
two are instructions written using RTL .If these two operations is to occur
simultaneously then which symbol will we use to separate them so that it
becomes a correct statement with the condition that two operations occur
simultaneously? ►
Arrow ¬ ►
Colon : ► Comma , (Page 69) ►
Parentheses () Question No: 7 – Prefetching can be considered a primitive form
of————- ing (Page 42) -processing
-execution Question No: 8 – The processor must have a way of saving information about
its state or context so that it can be restored upon return from the
————- Question No: 9 – Which
one of the following circuit design levels is called the gate level? ► (Page 22) ► ► ► Question No: 10 – __________ enable the input to the PC for
receiving a value that is currently on the internal processor bus. ► LPC (Page 172) rep ►
INC4 ►
LC ►
Cout 6 Question No: 11 – ________
operation is required to change the processor‟s state to a known, defined
value. ►
Change ► Reset (Page 194) rep ►
Update ►
None of the given Question No: 12 – There
are _________ types of reset operations in SRC ► Two (Page 195) ►
Three ►
Four ►
Five Question No: 13 – _____________
controller controls the sequence of the flow of microinstructions. ►
Multiplexer ► Microprogram (Page 225) ►
ALU ►
None of the given Question No: 14 – FALCON-A
processor bus has 16 lines or is 16-bits wide while that of SRC is __________
wide. ►
8-bits ►
24-bits ► 32-bits (Page 157) REP ►
64-bits Question No: 15 – Which of the following statement(s) is/are correct about Reduced
Instruction Set Computer (RISC) architectures. (i)
The typical RISC machine instruction set is small, and is usually a subject
of a CISC instruction set. (ii)
No arithmetic or logical instruction can refer to the memory directly. (iii)
A comparatively large number of user registers are available. (iv)
Instructions can be easily decoded through hard-wired control units. ►
(i) and (iii) only ►
(i), (iii) and (iv) ►
(i), (ii) and (iii) only ►
(i),(ii),(iii) and (iv) 7 Question No: 16 – Which
one of the following register holds the instruction that is being executed? ►
Accumulator ►
Address Mask ► Instruction Register (Page 152) ►
Program Counter CS501-Advance Computer Architecture Midterm Special 2006 Question No: 1 – _____________all
memory systems are dumb, in that they respond to only two commands: read or
write Virtually Computer Systems Design And Architecture, 2/E Logically Physically None
of These Question No: 2 – To
access an operand in memory, the CPU must first generate an address, which it
then issues to the __________ MEMORY Computer Systems Design And Architecture, 2/E REGISTER DATA
BUS ALL
OF ABOVE Question No: 3 – ___________
or Branch instructions affect the order in which instructions are performed,
or control the flow of the program Control Computer Systems Design And Architecture, 2/E DATA
MOVMENT Arithmetic LOGICAL 8 MIDTERM EXAMINATION FALL 2006 CS501 – ADVANCE COMPUTER ARCHITECTURE Question No: 1 – The
code size of 2-address instruction is ________________. ►
5 bytes ► 7 bytes (Page 36) ►
3 bytes ►
2 bytes Question No: 2 The
data movement instructions ___________ data within the machine and to or from
input/output devices. ►
Store ►
Load ►
Move ► None of Above (Page 141) Question No: 3 – Register-register
instructions use ____________ memory operands out of a total of 3 operands ►
1 ►
3 ► 0 (Page 37) ►
2 Question No: 4 – _____________all
memory systems are dumb, in that they respond to only two commands: read or
write. ► Virtually Computer Systems Design And Architecture, 2/E
Rep ►
Logically ►
Physically ►
None of Above Question No: 5 – Flip-flop
is a ____________device, capable of storing one bit of Information ► Bi-stable (Page 76) ►
Unit-stable ►
Stable ►
Storage 9 1 (Nov 13, ) Question # 1 of 10 – In
which one of the following addressing modes, the value to be stored in memory
is obtained by directly retrieving it from another memory location? ►Direct Addressing Mode ►Immediate
addressing mode ►Indirect
Addressing Mode ►Register
(Direct) Addressing Mode Question # 2 of 10 – Execution
time of a program with respect to the processor is calculated as: ►Execution
Time = IC x CPI x MIPS ►Execution Time = IC x CPI x T (Page 254) ►Execution
Time = CPI x T x MFLOPS ►Execution
Time = IC x T Question # 3 of 10 – An
“assembler” that runs on one processor and translates an assembly language
program written for another processor into the machine language of the other
processor is called a —————- ►compiler ►cross assembler (Page 26) ►debugger ►linker Question # 4 of 10 – What
functionality is performed by the instruction “lar R3, 36” of SRC? ►It
will load the register R3 with the contents of the memory location M [PC+36] ►It will load the register R3 with the relative
address itself (PC+36). (Page 48) ►It
will store the register R3 contents to the memory location M [PC+36] ►No
operation Question # 5 of 10 – Which
operator is used to „name‟ registers, or part of registers, in the Register
Transfer Language? Select
correct option: ►:= (Page 66) ►& ►% ►© 10 Question # 6 of 10 – What
is the working of Processor Status Word (PSW)? ►To hold the current status of the processor. (Page 28) ►To
hold the address of the current process ►To
hold the instruction that the computer is currently processing ►To
hold the address of the next instruction in memory that is to be executed Question # 7 of 10 – Almost
every commercial computer has its own particular ———- language ►3GL ►English
language ►Higher
level language ►assembly language (Page 25) Question # 8 of 10 – In
which of the following instructions the data move between a register in the
processor and a memory location (or another register) and are also called
data movement? ►Arithmetic/logic ►Load/store (Page 141) ►Test/branch ►None
of the given Question # 9 of 10 – What
functionality is performed by the instruction “str R8, 34” of SRC? ►It
will load the register R8 with the contents of the memory location M [PC+34] ►It
will load the register R8 with the relative address itself (PC+34). ►It will store the register R8 contents to the memory location M
[PC+34] (Page 48) ►No
operation Question # 10 of 10 – What
does the instruction “ldr R3, 58” of SRC do? ►It will load the register R3 with the contents of the memory
location M [PC+58] (Page 47) ►It
will load the register R3 with the relative address itself (PC+58). ►It
will store the register R3 contents to the memory location M [PC+58] ►No
operation 11 1 (23--) Question # 1 of 10 – Which
one of the following is the highest level of abstraction in digital design in
which the computer architect views the system for the description of system
components and their interconnections? ►Processor-Memory-Switch level (PMS level) (Page 22) ►Instruction
Set Level ►Register
Transfer Level ►None
of the given Question # 2 of 10 – Which
of the instruction is used to load register from memory using a relative
address? ►ld
instruction ►ldr instruction (Page 47) ►lar
instruction ►str
instruction Question # 3 of 10 – For
the __________ type instructions, we require a register to hold the data that
is to be loaded from the memory, or stored back to the memory ►Jump ►Control ►load/store (Page 89) ►None
of the given Question # 4 of 10 – The
CPU includes three types of instructions, which have different operands and
will need different representations. Which one of the instructions requires
two source registers? ►Jump
and branch format instructions ►Immediate
format instructions ►Register format instructions 12 2 ( 07, ) Question # 1 of 10 – What is the size of
the memory space that is available to FALCON-A processor? ►2^8
bytes ►2^16 bytes (Page 90) ►2^32
bytes ►2^64
bytes Question # 2 of 10 – How can we refer to
an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL? ►IR<16..0> ►IR<15..0> (Page 105) ►IR<16..1> ►IR<15..1> Question # 3 of 10 – Which one of the
following portions of an instruction represents the operation to be
performed? ►Address ►Instruction
code ►Opcode ►Operand (Page 134) Question # 4 of 10 – Identify
the opcode, destination register (DR), source registers (SA and SB i/e source
register A and source register B) from the following example. ADD R1, R2, R3 ►Opcode= R1, DR=ADD, SA=R2, SB=R3 ►Opcode= ADD, DR=R1, SA=R2, SB=R3 (Page 34) ►Opcode=
R2, DR=ADD, SA=R1, SB=R3 ►Opcode= ADD, DR=R3, SA=R2, SB=R1 Question # 5 of 10 – What
does the word „D‟ in the „D-flip-Flop‟ stands for? ►Data ►Digital ►Dynamic ►Double 13 Question # 6 of 10 – Which one of the
following is the code size and the Number of memory bytes respectively for a
2-address instruction? ►4
bytes, 7 bytes ►7
bytes, 16 bytes (Page 36) ►10
bytes, 19 bytes ►13
bytes, 22 bytes Question # 7 of 10 – Which of the following can be defined as an
address of the operand in a computer type instruction or the target address
in a branch type instruction? ►Base
address ►Binary
address ►Effective address ►All
of the given Question # 8 of 10 – Whic
of the following statements is/are true about RISC processors‟ claimed
advantages over CISC processors? (a) Keeping regularly accessed variables in
registers as opposed to keeping them in memory facilitates faster execution.
(b) RISC CPUs outperform CISC CPU‟s in procedural programming environments.
(c) Instruction pipelining has helped RISC CPU‟s to attain a target of 1
cycle per instruction. (d) It is easier to maintain the “family concept” in
RISC CPUs. ►
(a), (b) &(c) ►
(b), (c) & (e) ►
(c), (d) & (e) ► (a), (c) & (d) Question # 9 of 10 – Which
one of the following is/are the features of Register Transfer Language? 1. a) It is a symbolic
language 2. b) It is describing
the internal organization of digital computers 3. c) It is an
elementary operation performed (during one clock pulse), on the information
stored in one or more registers 4. d) It is high level
language ► (b) only ► (a)
& (b) only ► (a) ,(b) & (d) ► (b),(c) & (d) 14 Question # 10 of 10 – Motorola MC68000 is
an example of ———microprocessor. ►CISC (Page 148) ►RISC ►SRC ►FALCON Question # 1 of 10 – Which one of the
following registers holds the instruction that is being executed? ►Accumulator ►Address
Mask ►Instruction Register (Page 152) rep ►Program
Counter Question # 2 of 10 – The external
interface of FALCON-A consists of a ________ data bus. ►8-bit ►16-bit (Page 167) ►24-bit ►32-bit Question # 3 of 10 – In which one of the
following techniques, the time a processor spends waiting for instructions to
be fetched from memory is minimized? Select correct option: ►Perfecting ►Pipelining ►Superscalar
operation ►Speedup Question # 4 of 10 – ———–is the ability
of application software to operate on models of equipment newer than the
model for which it was originally developed. Select correct option: ►Backward
compatibility ►Data
migration ►Reverse
engineering ►Upward compatibility click here for def 15 Question # 5 of 10 – _________ control
signal allows the contents of the Program Counter register to be written onto
the internal processor bus. ►INC4 ►LPC ►PCout (Page 172) ►LC Question # 6 of 10 – Which one of the
following registers stores a previously calculated value or a value loaded
from the main memory? ►Accumulator ►Address
Mask ►Instruction
Register ►Program Counter Question # 7 of 10 – Computer system
performance is usually measured by the ————— ►Time to execute a program or program mix ►The
speed with which it executes programs ►Processor‟s
utilization in solving the problems ►Instructions
that can be carried out simultaneously Question # 8 of 10 – Which
one of the following register(s) that is/are programmer invisible and is/are
required to hold an operand or result value while the bus is busy
transmitting some other value? ►Instruction
Register ►Memory
address register ►Memory
Buffer Register ►Registers A and C (Page 152) Question # 9 of 10 – ————– performs the data operations as
commanded by the program instructions. ►Control (not sure) ►Data
path ►Structural
RTL ►Timing 16 Question # 10 of 10 – Which
one of the following register(s) contain(s) the address of the place the CPU
wants to work with in the main memory and is/are directly connected to the RAM
chips on the motherboard? ►Instruction Register ►Memory address register ►Memory
Buffer Register ►Registers
A and C |
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